1. Field of the Invention
The present invention relates to a microcomputer capable of outputting pulses, and, more particularly, to a microcomputer capable of executing interrupt processes corresponding to interrupt signals by halting the execution of predetermined processes currently executed when an arithmetic processing unit incorporated in the microcomputer receives trigger signals for the interrupt signals.
2. Description of the Prior Art
FIG.24 is a block diagram showing a configuration of a conventional microcomputer with a function to output pulses. In FIG. 24, the reference number 100 designates an arithmetic processing unit for executing predetermined various kinds of processes and interrupt processes according to an interrupt signal when receiving a trigger signal corresponding to this interrupt signal used for the interrupt process. The reference number 200 denotes a trigger circuit for generating and outputting the trigger signal to the arithmetic processing unit 100 and other sections. The reference number 300 indicates a group of data buses (hereinafter referred to only as the data bus) for data input/output among the arithmetic processing unit 100 and other devices, 400 designates a pulse width control register for receiving pulse width data transmitted from the arithmetic processing unit 100, for storing these data items, and for generating and outputting pulse width control signals corresponding to the received pulse width control data. The reference number 500 denotes a pulse switching control register for receiving and storing pulse switching data transmitted from the arithmetic processing unit 100, and for generating and outputting pulse switching signals corresponding to the received pulse switching data. The reference number 600 indicates a pulse output period control register for receiving and storing pulse output period data transmitted from the arithmetic processing unit 100, and for generating and outputting pulse output period signals corresponding to the received pulse output period data. The reference number 700 designates a data latch circuit for sampling the pulse output period signals based on the trigger signal outputted to the arithmetic processing unit 100 and for outputting a pulse output period synchronous signal. The reference number 800 denotes a pulse generation circuit (pulse generator) for continuously outputting pulses having a pulse width corresponding to the pulse width control signals transmitted from the pulse width control register 400. The reference number 900 designates an inverter for inverting the electrical level of the pulses output from the pulse generator 800, and 1000 denotes a NAND circuit for receiving both the inverted pulses and pulse switching signal transferred from the pulse switching control register 500, for performing inverted AND operation (or inverted logical sum operation) between them, and for outputting the result of the inverted AND operation as a first logical arithmetic signal. The reference number 1100 indicates an AND circuit for receiving the first logical arithmetic signal and the pulse output period synchronous signal and for performing logical AND operation (or logical sum operation) between them and for outputting the result of the logical arithmetic operation as a second logical arithmetic signal.
Next, a description will now be given of the operation of the conventional microcomputer capable of outputting pulses.
Firstly, the trigger circuit 200 generates and transfers a trigger signal to the arithmetic operation unit 100. When receiving the trigger signal, the arithmetic operation unit 100 halts the operation of current processes and then executes an interrupt process corresponding to the trigger signal as an interrupt signal. In the interrupt operation, the arithmetic operation unit 100 transfers various data items to the pulse width control register 400, the pulse switching control register 500, and the pulse output period register 600. Then, those registers 400, 500, and 600 store the data items transferred from the arithmetic operation unit 100. Then, the pulse generator 800 generates and outputs pulses having a constant pulse width according to the pulse width control signal from the pulse width control register 400. Those output signals as the pulses from the pulse generator 800 are transferred to the NAND circuit 1000 through the inverter 900. The NAND circuit 1000 outputs the first logical arithmetic signals having a waveform in which the pulses from the inverter 900 are subtracted per predetermined period. In addition to this, the AND circuit 1100 outputs the second logical arithmetic signals having a waveform in which the first logical arithmetic signals are subtracted per pulse output period synchronous signal that is synchronized with the latch signal from the data latch circuit 700. Those second logical arithmetic signals are provided to outside devices as output pulses of the microcomputer. Specifically, the trigger circuit 200 incorporates an internal timer (omitted from FIG. 24), the trigger circuit 200 generates and outputs the trigger signals according to output of the internal timer. For example, it is also acceptable in configuration to incorporate an input terminal through which external signals are inputted in the microcomputer. In this configuration, the trigger circuit 200 generates and outputs the trigger signals based on the receiving of external signals supplied through the input terminal.
Because the conventional microcomputer capable of outputting pulses has the above configuration, it is difficult to execute real time operation even if it is required to output pulses from the microcomputer in real time, namely it is difficult to switch the output pulse immediately, according to the receiving of the trigger signal transferred from the trigger circuit 200. Therefore, as a matter of course, it is required to generate and transfer the trigger signals to the arithmetic processing unit 100 by the trigger circuit 200 without any delaying of normal operations of the microcomputer. Accordingly, it is difficult to switch the output pulses at a high sped rate in the conventional microcomputer because the conventional microcomputer has the above configuration in which the output pulses are switched by the data replace operation described above. In addition, it is not possible to specify a timing of switching of the output pulses based on the data replace operations and it is also difficult to output a pulse train having a same pattern continuously based on a same control operation.
Furthermore, even if the interrupt process for outputting pulses occupies the operation of the arithmetic processing unit 100, or even if the priority level of the interrupt operation caused by the trigger circuit 200 is increased in order to eliminate the drawbacks described above, it is difficult to perform the pulse output operation in the microprocessor in real time by switching or changing the output pulses per very short time period, because a delay time from the time after the trigger circuit 200 outputs the trigger signal to the time of data switching or to the timing of switching of the output pulses is very long.
As described above, there is the drawback that it is difficult to change output pulses from the microcomputer in real time, namely immediately, according to switching of trigger signals without increasing of load of the arithmetic processing unit 100.